A conventional MPEG digital video encoder/decoder (CODEC) connects to a number input/output modules via a number of different size FIFO memories. Each of the FIFO memories connects to the conventional CODEC via a separate direct memory access (DMA) channel. The area used by the numerous memories can be large due to the overhead of address decoders, sense amplifiers and multiple read/write ports. The conventional architecture also adds complexity to the control logic of the CODEC and the procedures for testing the CODEC.
It would be desirable to connect a number of input/output modules to a MPEG digital video encoder/decoder via a single direct memory access channel.